Aug 10, 2005
Accent, ARM to show the new MSMV low power design flow at CDNLive!
Silicon Valley, September 12-14
and ARM Metro libraries.
Abstract
Today low power is more than ever a very important topic for integrated circuit design and the ability to address it at all levels is a key differentiating factor in the business of design services. At the silicon implementation level, voltage scaling is one of the most effective techniques to reduce power consumption.
Accent has set up and proven on a real design a physical design flow for low power ICs based on the Multiple Supply Multiple Voltage (MSMV) methodology: the flow is based on the Cadence Encounter platform and on the ARM Artisan Physical IP Metro Libraries on the TSMC cl013g process. The design proved that with the Metro Libraries and the Encounter tools it is possible to considerably reduce both static and dynamic power consumption (as estimated from real design activity information) by partitioning the design in several power domains, each with different supply voltage as needed to meet timing constraints.
Results (in WC conditions) show a decrease in both dynamic and leakage power consumption as high as 40% for the logic in voltage islands powered at 0.7V with respect to a baseline design implemented at 1.08V, at a cost of a small increase in area.
- Session 2.6
Wednesday, September 14
8:00am- 9:30am
Schedule and registration
To know how Multi-Supply Multi-Voltage design technique
can reduce power consumption of Your IC, just click
Source: Accent, ARM, Cadence
