Our expertise in managing leading-edge silicon technologies, along with our long track record in the design of full electronic systems and integration of multi-million gate heterogeneous ICs (SoC, ASIC, ASSP and Custom ICs), has led to more than 300 designs with a 98 percent first-time silicon success track record.
We have worked with a number leading silicon foundries and complex technologies including:
- TSMC, Chartered, SMIC
- CMOS, BCD, BiCMOS SiGE
- Process geometries down to 45 nm
In addition, Accent delivers tremendous expertise in a number of market spaces and the following design areas to provide complex integrated products that meet demanding performance requirements and significantly lower our customer's bill of materials.
Accent Design Services includes IC design from concept to RTL netlist and silicon implementation from RTL netlist to FPGA or GDSII
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Requirements Gathering
Accent works initially with its customers to understand all aspects of a product’s requirements. We then develop a product requirement checklist that serves as the basis for analysis and proposal of potential product performance and cost tradeoffs.
IP provided by the customer also undergoes the Accent IP qualification process identical to that used on the internal IP. Any quality gaps including integration ability and test coverage are identified with a recovery action plan provided by Accent, such as starting an IP redesign process.
Specification
System specification targets the system’s partition into HW/SW components to develop an architecture capable of satisfying its functional and performance requirements. Major activities involve architectural exploration and performance analysis by Accent architects together with the customer.
We account for target application software and Operating System constraints, with or without Real Time constraints, and explore a wide variety of hardware and software implementations that trade off design requirements, cost limitations and time-to-market, guaranteeing a low-risk, highly optimized solution. Typical deliverables include system specification, design and implementation plan.
Circuit and Logic Design
In this stage, Accent begins mapping a system specification to a physical implementation. Any IP which needs to be developed, integrated and procured is addressed and the activity is owned by Accent. Circuit design or redesign for AMS and RF blocks starts here. Mixed-mode simulation environments and test structures are finalized with planning for production coverage and risk-reliability trade-offs taking place.
Verification
Accent’s system integration and verification approach is based on different layers of abstraction and on the functional verification at hierarchical levels: block level, sub-system level, and system level. When block level and system level simulations are unable to capture all the complexities of the actual chip behavior, or they do not completely model the interactions between the chip and other system components and software, then the application code is run with SW simulation using HW acceleration or customized HW emulation boards.
Early system prototyping may also commence in this phase. This may be done by implementing a range of systems, from software-based simulators to a mix of FPGA and silicon based hardware. This enables us to model interactions between the chip and other system components while running actual application code.
Logic Implementation
IC Physical Design encompasses RTL implementation flow through GDSII sign-off, mapping the design onto the target silicon technology and releasing the PG tape for the foundry. The first phase, or the Logic Implementation from RTL to netlist, includes RTL qualification, synthesis, Design for Testability (DFT) and Timing Analysis.
We understand the dependencies of synthesis strategy and test coverage with design structure and organization. When designs fall short in performance in this stage, we can often restructure synthesis targets to boost results. If this is not possible, Accent will employ redesign to achieve performance expectations.
Physical Implementation
Physical Implementation spans gate level netlist to physical layout including netlist qualification, floorplanning, place and route, physical verification, parasitic extraction and post-layout timing verification. We use leading-edge EDA technology and our robust design methodology to guarantee quality results and a predictable implementation cycle time.
Physical implementation begins after a preliminary gate level netlist is available. Accent creates a physical prototype in an extremely short time to assess design feasibility, including floorplan setup, routability and timing closure, and to estimate the silicon area. With a quick turn-around, Accent can verify and guarantee that, once integrated on silicon, the design will fully meet its performance and cost objectives.
